Design a serial adder circuit using Verilog. The circuit should add two 8-bit numbers, A and B. The result should be stored back into the A register. Use the diagram below to guide you. Hint: Write one module to describe the datapath and a second module to describe the control.

Mini Project on 4 BIT SERIAL MULTIPLIER • 1. Page 1 of 19 4 BIT SERIAL MULTIPLIER A Project Based LAB Dissertation LAB Title: Design with CPLDs and FPGAs Submitted by Mr.

J.NAGA SAI (Reg. 150040317) LAB Instructors Mr. B.Kali vara Prasad (Section Instructor) Mr. Narasimha Nayak Dr.A.

Kiran Kumar Mr.M.Venkateswara rao Department of ECE, KL University Vaddeswaram, Guntur, AP – 522502 A.Y. 2016-17 • Page 2 of 19 Department of Electronics and Communication Engineering KL University Vaddeswaram, Guntur, AP – 522502 CERTIFICATE This is to certify that the project entitled '4-BIT SERIAL MULTIPLIER ' is a piece of work done by J.NAGA SAI(150040317) students of II B.Tech. (ECE), during the First semester of academic year 2016-2017, of Department of Electronics and Communication Engineering of KL University, Vaddeswaram, Guntur, A.P., INDIA. Course Coordinator Signature of the H.O.D (Dr.

Fazal Noorbasha) (Dr.ASCS Sastry) • Page 3 of 19 Declaration by the Students We declare that the project entitled, “4-BIT SERIAL MULTIPLIER” is our own work conducted under the esteemed guidance of Mr. B.Kali vara Prasad (Section Instructor) Mr. Narasimha Nayak Dr.A. Kiran Kumar,Mr.M.Venkateswara rao at the Department of Electronics and Communication Engineering of KL University, Vaddeswaram, Guntur, A.P., INDIA.

J.NAGA SAI (Reg. 150040317) • Page 4 of 19 Acknowledgements Working on this Project based Lab is certainly a memorable and enjoyable event in our life.

We have learned a lot of interesting new things that have broadened my view of the technology field. In here, we would like to offer our appreciation and thanks to several grateful and helpful individuals. Without them, this work could not have been completed and the experience would not be so enjoyable. We are very grateful to our esteemed Professors Dr.

Fazal Noorbasha (Course Coordinator), Mr.B.Kali vara Prasad (Section Instructor)Mr. Narasimha NayakDr.A.

Kiran Kumar Mr.M.Venkateswara raoDepartment of ECE, KL University, Vaddeswaram, Guntur, A.P., INDIA, for their valuable guidance and creative suggestions that helped us to complete this Lab project. Furthermore, we want to offer our thanks to Dr. ASCS Sastry, Professor & Head, Department ECE, KL University, Vaddeswaram, Guntur, A.P., INDIA, for providing the required facilities to carry out the project work successfully. We would like to thank all those helped us directly or indirectly during this project work. J.NAGA SAI (Reg.