Webopedia's list of Data File Formats and File Extensions makes it easy to look through thousands of extensions and file formats to find what you need. Bluespec System Verilog file.bt! BitTorrent Partial Download file.btm: Batch To Memory batch file (4DOS). (Windows 3.x) Compiler script file (clip list) (Clipper 5).clpi: Blue-ray Disc. GitHub is home to over 28 million developers working together to host and review code, manage projects, and build software together. Clone or download. A tutorial for learning the Bluespec BSV HLHDL (High Level Hardware Design. A commercial implementation of BSV (a compiler from BSV into Verilog) has been.

RISCV_Piccolo_v1 Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

MIT License (see LICENSE.txt) Introduction This is a preliminary release of Bluespec Inc.' S Piccolo, which is a an implementation of the RISC-V Instruction Set Architecture (ISA).

• RV32IM variant of the RISC-V ISA. Crashday isohunt. • Simple 3-stage in-order pipeline, target for low-resource applications, such as FPGA softcores. • User- and Machine-mode privilege levels. • No memory management, no floating point. This repository contains all the Verilog source files for the Piccolo CPU, as well as for surrounding modules that enable system-level execution ( Top_Sim_Standalone, SoC_Top, Sim_Driver, ICache, DCache, Fabric, Mem_Controller, Mem_Model, UART). In addition, this repository contains two pre-built simulation executables that you can run immediately (on 64-bit Linux platforms) built from the same source code. One uses Bluespec's Bluesim simulator, and the other uses the Verilator open source Verilog simulator.

Finally, this repository contains some pre-compiled RISC-V ELF binaries for C and RISC-V assembly language programs, compiled using the RISC-V gcc toolchain. You can run the simulators on these ELF files, i.e., you will be simulating a CPU-Caches-Fabric-Memory-UART 'SoC' system, where the CPU is the Piccolo RISC-V CPU, and it is executing one of the ELF binaries. If you have the RISC-V gcc toolchain (from riscv.org) you should be able to compile other programs into ELF executables and run them on these simulators. The Makefiles in the Bluesim/ and Verilogsim directories provide examples of how to invoke the simulator on an executable. NOTE: these simulators have been compiled to run on 64-bit x86 Linux platforms only (such as Ubuntu and Debian).

We have no plan to produce versions for other platforms (e.g., Windows, Mac OS). Repository contents: • Bluesim/ Contains a pre-built Linux executable using Bluespec, Inc.' S Bluesim simulator.

The Makefile allows running the simulator on any of the pre-compiled ELF files in Programs/ directory. For example, $ make do_test_hello runs the 'Hello World!' • Verilogsim/ Contains a pre-built Linux executable that is a Verilog simulator built using Verilator. The Makefile allows running the simulator on any of the pre-compiled ELF files in Programs/ directory. For example, $ make do_test_hello runs the 'Hello World!' • verilog/ Verilog RTL from which the Verilog simulation executable was built.

This Verilog RTL is not hand-written, but generated from Bluespec BSV sources (not included) by Bluespec's bsc compiler. It's moderately readable (YMMV).

• Cpp_src/ Contains the Verilator top-level driver sim_main.cpp and a few other C++ files that are imported by the Verilog code. • Makefile_verilator Makefile to rebuild the Verilog simulation executable using Verilator (see below).

This will allow you to tell Verilator to incorporate VCD dumping, profiling, etc. • RISCV_Programs/ • C_tests_RV32IM/ • asm_tests_RV32IM/ These contain a number of sub-directories (e.g., 'hello/', containing a 'Hello World!' Each directory contains a.c (C) or.S (assembly) source file, a pre-compiled RISC-V RV32IM ELF executable, and a.text dis-assembly of the ELF file. Running the Bluesim simulator on RISV-V ELF files You should be in the Bluesim directory: $ cd Bluesim To run an individual program, e.g., 'Hello World!' : $ make do_test_hello To run all programs (file sample_transcript is a transcript of this): $ make do_tests If you set the environment variable SIM_VERBOSITY (to 1, 2.) it will produce increasingly detailed simulation traces indicating activity on a clock-by-clock basis in the CPU pipeline, caches, interconnect fabric and memory controller. Note: The make commands invoke the Bluesim executable: $ top_Sim_Standalone_exe If you provide the flag -V it will dump VCDs waveforms to the file dump.vcd.